View ADP3331_21265.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
Adjustable Output Ultralow IQ, 200 mA, SOT-23, anyCAPTM Low Dropout Regulator ADP3331
FUNCTIONAL BLOCK DIAGRAM
Q1 THERMAL PROTECTION ERR Q2 SD DRIVER gm IN OUT
FEATURES High Accuracy Over Line and Load: 0.7% @ +25 C, 1.4% Over Temperature Ultralow Dropout Voltage: 140 mV (Typ) @ 200 mA Can Be Used as a High Current (>1 A) LDO Controller Requires Only CO = 0.47 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: <2 A 2.6 V to 12 V Supply Range 1.5 V to 10 V Output Range -40 C to +85 C Ambient Temperature Range Ultrasmall Thermally Enhanced Chip-on-LeadTM SOT-23-6 Lead Package APPLICATIONS Cellular Telephones Notebook, Palmtop Computers Battery Powered Systems PCMCIA Regulator Bar Code Scanners Camcorders, Cameras
ADP3331
CC FB
BANDGAP REF
GND
ERR
EOUT R3 330k VOUT R1 + C2 0.47 F
ADP3331
VIN C1 0.47 F + SD IN OUT FB GND ON OFF
R2
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
The ADP3331 is a member of the ADP330x family of precision low dropout anyCAP voltage regulators. The ADP3331 operates with an input voltage range of 2.6 V to 12 V and delivers a load current up to 200 mA. The ADP3331 stands out from the conventional LDOs with a novel architecture and an enhanced process that enables it to offer performance advantages and higher output current than its competition. Its patented design requires only a 0.47 F output capacitor for stability. This device is insensitive to capacitor Equivalent Series Resistance (ESR), and is stable with any good quality capacitor, including ceramic (MLCC) types for space restricted
applications. The ADP3331 achieves exceptional accuracy of 0.7% at room temperature and 1.4% overall accuracy over temperature, line and load variations. The dropout voltage of the ADP3331 is only 140 mV (typical) at 200 mA. This device also includes a safety current limit, thermal overload protection and a shutdown feature. In shutdown mode, the ground current is reduced to less than 2 A. The ADP3331 has ultralow quiescent current 34 A (typical) in light load situations. The SOT-23-6 package has been thermally enhanced using Analog Device's proprietary Chip-on-Lead feature to maximize power dissipation.
anyCAP and Chip-on-Lead are trademarks of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADP3331-SPECIFICATIONS noted)
Parameter OUTPUT VOLTAGE ACCURACY HIGH OUTPUT VOLTAGE RANGE
3
(@TA = -40 C to +85 C, VIN = 7 V, CIN = 0.47 F, COUT = 0.47 F, unless otherwise
1, 2
Symbol
Conditions VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM 2.35 V, IL = 0.1 mA to 200 mA, TA = +25C VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM 2.35 V, IL = 0.1 mA to 150 mA, TA = -40C to +85C VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM 2.35 V, IL = 0.1 mA to 200 mA, TA = -20C to +85C VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 200 mA, TA = +25C VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 150 mA, TA = -40C to +85C VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 200 mA, TA = -20C to +85C
Min
Typ
Max
Units
-0.7
+0.7
%
-1.4
+1.4
%
-1.4
+1.4
%
OUTPUT VOLTAGE ACCURACY3 LOW OUTPUT VOLTAGE RANGE
-0.7
+0.7
%
-1.4
+1.4
%
-1.4 0.06 0.04 1.6 1.2 0.4 34 37 0.14 0.11 0.042 0.025 300 47 95 2.0
+1.4
% mV/V mV/mA
LINE REGULATION LOAD REGULATION GROUND CURRENT
VO VIN VO IL IGND
VIN = VOUTNOM +0.25 V to 12 V TA = +25C IL= 0.1 mA to 200 mA TA = +25C IL = 200 mA, TA = -20C to +85C IL = 150 mA IL = 50 mA IL = 0.1 mA VIN = VOUTNOM - 100 mV IL = 0.1 mA VOUT = 98% of V OUTNOM IL = 200 mA, TA = -20C to +85C IL = 150 mA IL = 10 mA IL = 1 mA VIN = VOUTNOM + 1 V f = 10 Hz-100 kHz, CL = 10 F IL = 200 mA, CNR = 10 nF, VOUT = 3 V f = 10 Hz-100 kHz, CL = 10 F IL = 200 mA, CNR = 0 nF, VOUT = 3 V ON OFF 0 < SD 12 V 0 < SD 5 V SD = 0 V, VIN = 12 V
4.0 3.1 1.1 50 55 0.23 0.17 0.06 0.052
mA mA mA A A V V V V mA V rms V rms
GROUND CURRENT IN DROPOUT DROPOUT VOLTAGE
IGND VDROP
PEAK LOAD CURRENT OUTPUT NOISE
ILDPK VNOISE
SHUTDOWN THRESHOLD SHUTDOWN PIN INPUT CURRENT GROUND CURRENT IN SHUTDOWN MODE
VTHSD ISD
0.4 1.9 1.4 0.01 9 6 2
V V A A A
IGNDSD
-2-
REV. 0
ADP3331
Parameter OUTPUT CURRENT IN SHUTDOWN MODE ERROR PIN OUTPUT LEAKAGE ERROR PIN OUTPUT "LOW" VOLTAGE Symbol IOSD IEL VEOL Conditions TA = +25C @ VIN = 12 V TA = +85C @ V IN = 12 V VEO = 5 V ISINK = 400 A 0.19 Min Typ Max 1 2 1 0.40 Units A A A V
NOTES 1 Ambient temperature of +85C corresponds to a junction temperature of +125C under typical full load test conditions. 2 Application stable with no load. 3 Assumes the use of ideal resistors. Overall accuracy also depends on the tolerance of the external resistors used to set the output voltage. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . -0.3 to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . . . -0.3 to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . -40C to +85C Operating Junction Temperature Range . . . -40C to +125C JA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . 165C/W JA (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . 190C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
Pin 1 2 3
Name OUT IN ERR
Function Output of the Regulator. Bypass to ground with a 0.47 F or larger capacitor. Regulator Input. Open Collector Output that goes low to indicate that the output is about to go out of regulation. Ground. Feedback Input. Connect to an external resistor divider which sets the output voltage. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin.
PIN CONFIGURATION
4 5
GND FB
ORDERING GUIDE
6 Marking Code L9B
SD
Model ADP3331ART
Output Voltage ADJ
Package Option RT-6 (SOT-23-6)
OUT
1
ADP3331
6 5
SD
FB TOP VIEW ERR 3 (Not to Scale) 4 GND
IN 2
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3331 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-3-
ADP3331-Typical Performance Characteristics
3.010 3.008 VOUT = 3.0V OUTPUT VOLTAGE - Volts 3.005 3.004 3.003 3.002 3.001 3.000 2.999 2.998 2.997 2.996 2.995 11 12 2.994 0 25 50 75 100 125 150 175 200 OUTPUT LOAD - mA VOUT = 3.0V VIN = 7V GROUND CURRENT - A 45 VOUT = 3V 40 35 30 25 20 15 10 5 0 0 2 4 6 8 10 INPUT VOLTAGE - Volts 12 IL = 0 A IL = 100 A
OUTPUT VOLTAGE - Volts
3.006 3.004 3.002 3.000 2.998 2.996 2.994 2.992 IL = 200mA IL = 150mA IL = 0mA IL = 10mA IL = 50mA IL = 100mA
2.990 3.25 4
5
6 7 8 9 10 INPUT VOLTAGE - Volts
Figure 2. Line Regulation Output Voltage vs. Supply Voltage
Figure 3. Output Voltage vs. Load Current
Figure 4. Ground Current vs. Supply Voltage
1.6 VIN = 7V 1.4 GROUND CURRENT - mA 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 OUTPUT LOAD - mA 200
0.4 IL = 0mA GROUND CURRENT - mA 0.3 OUTPUT VOLTAGE - % IL = 50mA
0.2 IL = 150mA 0.1 IL = 200mA 0.0
-0.1 -45 -25 -5 15 35 55 75 95 115 135 JUNCTION TEMPERATURE - C
3.0 VIN = 7V 2.8 IL = 200mA 2.6 2.4 2.2 IL = 150mA 2.0 1.8 IL = 100mA 1.6 1.4 1.2 1.0 0.8 0.6 0.4 IL = 50mA 0.2 IL = 0mA 0 -45 -25 -5 15 35 55 75 95 115 135 JUNCTION TEMPERATURE - C
Figure 5. Ground Current vs. Load Current
Figure 6. Output Voltage Variation % vs. Junction Temperature
Figure 7. Ground Current vs. Junction Temperature
250
INPUT/OUTPUT VOLTAGE - Volts
3.5 3.0 2.5 2.0 1.5
VIN - Volts VOUT - Volts
INPUT/OUTPUT VOLTAGE - mV
200
VOUT = 3V SD = VIN RL = 15
CL = 0.47 F 3 2 1 0 10 5 0 0 100 200 300 TIME - s 400 500 CL = 10 F VIN = 7V VOUT = 3V SD = VIN RL = 15
150
100
1.0 0.5 0 0 1.0 2.0 3.0 TIME - Sec 4.0 5.0
50
0
0
25
50 75 100 125 150 175 200 OUTPUT LOAD - mA
Figure 8. Dropout Voltage vs. Output Current
Figure 9. Power-Up/Power-Down
Figure 10. Power-Up Response
-4-
REV. 0
ADP3331
3.100 3.040 VOUT - Volts VOUT - Volts 3.000 2.960 2.920 VOUT = 3V RL = 15 CL = 0.47 F 3.040 3.000 2.960 2.920 VOUT = 3V RL = 15 CL = 10 F Volts 3.050 3.000 2.950 2.900 200 VIN - Volts VIN - Volts mA 7.5 7.0 0 100 200 300 TIME - s 400 500 7.5 7.0 0 100 200 300 TIME - s 400 500 100 20mA 0 VIN = 7V VOUT = 3V CL = 0.47 F
0
200
400
600
800
1000
TIME - s
Figure 11. Line Transient Response
Figure 12. Line Transient Response
Figure 13. Load Transient Response
Volts
3.100 3.050 Volts 3.000 2.950 2.900 200 mA 100 20mA 0 VIN = 7V VOUT = 3V CL = 10 F
3 0 500 400 300
VOUT 3 2 VOUT 1 IOUT Volts 0 VERR 3 0 2 VSD 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TIME - Sec
VIN = 7V VOUT = 3V CL = 10 F RL = 15
mA 200 100 VIN = 7V 0
0
200
400
600
800
1000
0
200
TIME - s
400 600 TIME - s
800
1000
Figure 14. Load Transient Response
Figure 15. Short Circuit Current
Figure 16. Turn On-Turn Off Response
0 VOUT = 3.0V -10 RIPPLE REJECTION - dB -20 -30 -40 -50 -60 -70 -80 -90 10 100 CL = 10 F IL = 200mA CL = 10 F IL = 0.1mA 1k 10k 100k FREQUENCY - Hz 1M 10M CL = 0.47 F IL = 200mA CL = 0.47 F IL = 0.1mA RMS NOISE - V
160 140 VOLTAGE NOISE SPECTRAL DENSITY - V/ Hz 120
IL = 200mA
1 CL = 0.47 F CNR = 0 CL = 10 F CNR = 0 CL = 0.47 F CNR = 10nF 0.1 CL = 10 F CNR = 10nF
100 80 60 40 20 0 0
IL = 0mA WITH NOISE REDUCTION IL = 0mA IL = 200mA WITH NOISE REDUCTION
VOUT = 3.0V IL = 200mA 40 50 0.01 10 100 1k 10k FREQUENCY - Hz 100k 1M
10
20 30 CL - F
Figure 17. Power Supply Ripple Rejection
Figure 18. RMS Noise vs. CL (10 Hz-100 kHz)
Figure 19. Output Noise Density
REV. 0
-5-
ADP3331
THEORY OF OPERATION
The new ADP3331 anyCAP LDO uses a single control loop for both regulation and reference functions as shown in Figure 20. The output voltage is sensed by an external resistive voltage divider consisting of R1 and R2. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier.
INPUT Q1 COMPENSATION CAPACITOR PTAT VOS R4 OUTPUT ATTENUATION (VBANDGAP/VOUT) R3 D1 (a) PTAT CURRENT R1 CLOAD RLOAD R2
ESR. The innovative design allows the circuit to be stable with just a small 0.47 F capacitor on the output. Additional advantages of the pole-splitting scheme include superior line noise rejection and very high regulator gain. The high gain leads to excellent regulation, and 1.4% accuracy is guaranteed over line, load and temperature. Additional features of the circuit include current limit, thermal shutdown and an error flag. Compared to standard solutions that give a warning after the output has lost regulation, the ADP3331 provides improved system performance by enabling the ERR pin to give a warning just before the device loses regulation. As the chip's temperature rises above +165C, the circuit activates a soft thermal shutdown to reduce the current to a safe level. The thermal shutdown condition is indicated by the ERR signal going low.
APPLICATION INFORMATION Capacitor Selection
NONINVERTING WIDEBAND DRIVER
gm
ADP3331
GND
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature-proportional input "offset voltage" that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a "virtual bandgap" voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values are chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider so that the error resulting from the base current loading in conventional circuits is avoided. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type and ESR of the load capacitor. Most LDOs place strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of the load capacitance and resistance. Moreover, the ESR value required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. This is no longer true with the ADP3331. It can be used with any good quality capacitor, with no constraint on the minimum
Output Capacitor: The stability and transient response of the LDO is a function of the output capacitor. The ADP3331 is stable with a wide range of capacitor values, types and ESR (anyCAP). A capacitor as low as 0.47 F is all that is needed for stability; larger capacitors can be used if high current surges on the output are anticipated. The ADP3331 is stable with extremely low ESR capacitors (ESR 0), such as Multilayer Ceramic Capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types fall below the minimum over temperature or with DC voltage. Input Capacitor: An input bypass capacitor is not strictly required but it is recommended in any application involving long input wires or high source impedance. Connecting a 0.47 F capacitor from the input to ground reduces the circuit's sensitivity to PC board layout and input transients. If a larger output capacitor is necessary, a larger value input capacitor is also recommended. Noise Reduction Capacitor: A noise reduction capacitor can be used to reduce the output noise by 6 dB to 10 dB. This capacitor limits the noise gain when connected between the feedback pin (FB) and the output pin (OUT) as shown in Figure 21. Low leakage capacitors in the 10 pF to 500 pF range provide the best performance. Since FB is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible and long PC board traces are not recommended. When adding a noise reduction capacitor, use the following guidelines: * Maintain a minimum load current of 1 mA when not in shutdown * For CNR values greater than 500 pF, add a 100 k series resistor (RNR). It is important to note that as CNR increases, the turn-on time will be delayed. With CNR values greater than 1 nF, this delay may be on the order of several milliseconds.
-6-
REV. 0
ADP3331
ERR EOUT R3 R NR C NR VOUT +C2 0.47 F
ADP3331
OUT VIN C1 + 0.47 F IN SD FB GND
divider network to achieve the best performance. Using standard values as shown in Table I will sacrifice some temperature stability.
Output Current Limit
R1
R2
The ADP3331 is short circuit protected by limiting the pass transistor's base drive current. The maximum output current is limited to about 300 mA.
Thermal Overload Protection
ON OFF
Figure 21. Noise Reduction Circuit
Output Voltage
The ADP3331 has an adjustable output voltage that can be set by an external resistor divider. The output voltage will be divided by R1 and R2, and then fed back to the FB pin. Refer to Figure 21. In order to have the lowest possible sensitivity of the output voltage to temperature variations, it is important that the parallel resistance of R1 and R2 is always 230 k: R1 x R2 = 230 k R1 + R2 Also, for the best accuracy over temperature the feedback voltage should set for 1.204 V: R2 VOUT = VFB R1 + R2 where VOUT is the desired output voltage and VFB is the "virtual bandgap" voltage. Note that VFB does not actually appear at the FB pin due to loading by the internal PTAT current. Combining the above equations and solving for R1 and R2 gives the following formulas: V R1 = 230 OUT k VFB R2 = 230 k VFB 1 - V OUT
The ADP3331 is protected against damage due to excessive power dissipation by its thermal overload protection circuit. Thermal protection limits the die temperature to a maximum of +165C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where the die temperature starts to rise above +165C, the output current will be reduced until the die temperature has dropped to a safe level. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, the device's power dissipation should be externally limited so that the junction temperature will not exceed 125C.
Chip-on-Lead
The ADP3331 uses a patented Chip-on-Lead package design to ensure the best thermal performance in an SOT-23 footprint. The standard SOT-23 depends on the majority of the heat to flow out of the ground pin. The Chip-on-Lead package uses an electrically isolated die attach, which allows all the pins to contribute to heat conduction. This technique reduces the thermal resistance to 190C/W on a 2-layer board as compared to >230C/W for a standard SOT-23 lead frame. Figure 22 shows the difference between the standard SOT-23 and the Chip-onLead lead frames.
SILICON DIE
SILICON DIE WITH ELECTRICALLY ISOLATED DIE ATTACH NORMAL SOT-23-6 PACKAGE
THERMALLY ENHANCED CHIP-ON-LEAD PACKAGE
Figure 22. Chip-on-Lead Package
Calculating Junction Temperature
The output voltage can be adjusted to any voltage from 1.5 V to 10 V. For example, the Feedback Resistor Selection Table shows some representative feedback resistor values for output voltages in the specified range.
Table I. Feedback Resistor Selection
Device power dissipation is calculated as follows: PD = (VIN - VOUT) ILOAD + (VIN ) IGND Where ILOAD and IGND are load current and ground current, VIN and VOUT are the input and output voltages respectively. Assuming the worst case operating conditions are ILOAD = 200 mA, IGND = 4 mA, V IN = 4.2 V and VOUT = 3.0 V, the device power dissipation is: PD = (4.2 V - 3.0 V) 200 mA + (4.2 V) 4 mA = 257 mW The proprietary package used on the ADP3331 has a thermal resistance of 165C/W when placed on a 4-layer board, and 190C/W when placed on a 2-layer board. This allows the ambient temperature to be significantly higher for a given power dissipation than with a standard package. Assuming a 4-layer board, the junction temperature rise above ambient will be approximately equal to: TJA = 0.257 W x 165C/W = 42.4C -7-
VOUT 1.5 V 1.8 V 2.2 V 2.7 V 3.3 V 5V 9V
R1 (1% Resistor) 243 k 340 k 422 k 511 k 634 k 953 k 1.00 M
R2 (1% Resistor) 1.00 M 698 k 511 k 412 k 365 k 301 k 154 k
Output voltages above 5 V and below 1.6 V will require nonstandard resistor values or adding an additional resistor to the REV. 0
ADP3331
To limit the junction temperature to 125C, the maximum allowable ambient temperature is: TA(MAX) = +125C - 42.4C = +82.6C
Shutdown Mode
conjunction with the preload and noise reduction capacitor. Further increases in the output capacitance may be acceptable if the output already has a sizable load during start-up.
Higher Output Current
Error Flag Dropout Detector
VIN = 3.3V C1 47 F
MJE253* R1 50
VOUT = 1.8V @ 1A
The ADP3331 will maintain its output voltage over a wide range of load, input voltage, and temperature conditions. If the output is about to lose regulation, due to the input voltage approaching the dropout level, the error flag will be activated. The ERR output is an open collector, which will be driven low. Once set, the ERR flag's hysteresis will keep the output low until a small margin of operating range is restored either by raising the supply voltage or reducing the load.
Low Voltage Applications
IN
OUT C2 10 F FB 340k
ADP3331
SD GND *REQUIRES HEAT SINK
ERR
698k
In applications where the output voltage is 2.2 V or less, the ADP3331 may begin to exhibit some turn-on overshoot. The degree of overshoot is determined by several factors: the output voltage setting, the output load, the noise reduction capacitor, and the output capacitor. The output voltage setting is determined by the application and cannot be tailored for minimum overshoot. In general, for output voltages 2.2 V or less, the overshoot becomes larger as the output voltage decreases. The output load is also determined by the system requirements. However, if the ADP3331 has no load on the output during start-up, a small amount of preload can be added to minimize overshoot. A preload of 2 A to 20 A is recommended. A noise reduction capacitor, if not already being used, is suggested to reduce the overshoot. Values in the range of 10 pF to 100 pF works best along with the preload suggested previously. The output capacitor can be adjusted to minimize the overshoot. Values in the 0.47 F to 1.0 F range should be used in
Figure 23. High Output Current Linear Regulator
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed circuit boards: 1. PC board traces with larger cross sectional areas will remove more heat from the ADP3331. For optimum heat transfer, specify thick copper and use wide traces. 2. The thermal resistance can be decreased by approximately 10% by adding a few square centimeters of copper area to the lands connected to the pins of the LDO. 3. The feedback pin is a high impedance input, and care should be taken when making a connection to this pin. The voltage setting resistors and noise reduction network must be located as close as possible. Long PC board traces are not recommended. Avoid routing traces near possible noise sources.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm). PRINTED IN U.S.A.
0.022 (0.55) 0.014 (0.35)
6-Lead Surface Mount RT-6 (SOT-23-6)
0.122 (3.10) 0.106 (2.70)
0.071 (1.80) 0.059 (1.50) PIN 1
6 1
5 2
4 3
0.118 (3.00) 0.098 (2.50)
0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.035 (0.90) 0.059 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE 10 0.009 (0.23) 0 0.003 (0.08)
-8-
REV. 0
C3624-2.5-6/99
Applying a TTL level high signal to the shutdown (SD) pin, or tying it to the input pin, will turn the output ON. Pulling the SD to 0.4 V or below, or tying it to ground, will turn the output OFF. In shutdown mode, the quiescent current is reduced to less than 1 A.
The ADP3331 can source up to 200 mA without any heat sink or pass transistor. If higher current is needed, an appropriate pass transistor can be used, as in Figure 23, to increase the output current to 1 A.

▲Up To Search▲

Price & Availability of ADP3331

	To Download ADP3331 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .